An internal oscillator is usually used in the integrated circuit for providing a system clock. However, because the components and the wires in the internal oscillator all have temperature properties, the frequency of the internal oscillator changes once the operating temperature changes.
A ring oscillator is usually served as a constituent circuit of the internal oscillator. Because the MOS device has the property of the positive temperature coefficient in itself, the frequency of the ring oscillator has the following properties when the temperature changes. When the temperature increases, the frequency become lower because of an increment of the internal resistance of the MOS device. Conversely, when the temperature decreases, the frequency become faster.
Please refer to FIG. 1, which is a schematic diagram showing a conventional internal oscillator 10. As shown, the internal oscillator 10 includes a ring oscillator 12 and an output unit 13. The ring oscillator 12 includes odd-number stages of inverter circuits 121, 122, 123, . . . , 128 and 129. An output terminal K9 of the ring oscillator 12 is electrically connected to an input terminal K0 of the inverter circuit 121, which causes an output signal VA9 of the ring oscillator 12 to be fed back to the input terminal K0 of the inverter circuit 121. Besides, an input terminal KA of the inverter circuit 121 receives an enable signal EN.
An output signal VA1 of the inverter circuit 121 has a delay and an inversion in comparison with the output signal VA9 of the inverter circuit 129. An output signal VA2 of the inverter circuit 122 has a delay and an inversion in comparison with the output signal VA1 of the inverter circuit 121. Similar scheme is applicable to two output signals of every two adjacent stages. Therefore, the output signal VA9 of the ring oscillator 12 has an oscillation frequency f1.
The output unit 13 includes two NOT gates connected in series, receives the output signal VA9, and produces a clock signal CLK1, wherein the clock signal CLK1 may have the oscillation frequency f1 in an ideal state.
Please refer to FIG. 2(a), which is a schematic diagram showing another conventional internal oscillator 20. As shown, the internal oscillator 20 includes a reference circuit 21, a ring oscillator 22 and an output unit 23. The reference circuit 21 includes an NMOS transistor 211, a resistor R2 with a positive temperature coefficient, and a PMOS transistor 213. A gate G of the PMOS transistor 213 receives a control signal V22, and a reference current i21 flows through the PMOS transistor 213, the resistor R2 and the NMOS transistor 211.
The ring oscillator 22 includes odd-number stages of inverter circuits 221, 222, 223, . . . , 228 and 229, and each (such as 221) of the inverter circuits 221, 222, 223, . . . , 228 and 229 includes the same structure. The ring oscillator 22 produces an output signal VB9 having an oscillation frequency f2. The inverter circuit 221 includes an NMOS transistor 2211, a PMOS transistor 2212 and a capacitor C21, and produces an output signal VB1. The output signal VB9 of the ring oscillator 22 is fed back to a gate of the PMOS transistor 2212. In order to achieve the required oscillation frequency f2 in a smaller amount of stages, a capacitor (e.g. C21) is added to each inverter (e.g. 221) for increasing a delay time between every two sequential stages of inverters.
The NMOS transistor 211 of the reference circuit 21 and an NMOS transistor (e.g. 2211) of each inverter (e.g. 221) constitute a current mirror. Therefore, plural currents i21, IB1, IB2, IB9 have a relation of i21=n*IB1=n*IB2=n*IB9, wherein n is a proportional coefficient. The reference circuit 21 controls a current (e.g. IB1), flowing in the each inverter (e.g. 221), to reach that the current is less influenced from the voltage drift. Besides, the reference current source circuit 21 utilizes the resistor R2 to adjust the oscillation frequency f2 of the ring oscillator 22.
The output unit 23 includes an NAND gate 231 ant an NOT gate 232. An input terminal M1 of the NAND gate 231 receives the output signal VA9. An input terminal M2 of the NAND gate 231 receives an enable signal V2A. The NOT gate 232 produces a clock signal CLK2, wherein the clock signal CLK2 may have the oscillation frequency f2 in an ideal state.
The common MOS device or the resistor R2 used in the reference circuit 21 mostly exhibits the property with a positive temperature coefficient in the semiconductor manufacturing process; i.e., the higher the temperature, the larger the resistance effect thereof, and the smaller on the contrary. Therefore, this property can cause the currents, flowing through various devices, to decrease when the temperature increases.
From the formula Q=CV=IT for the electric charge and the formula F=1/T for the frequency, a formula F=I/CV=1/RC is obtained, wherein the symbols C, V, T and R denote the capacitance, the voltage, the period and the resistance respectively. Please refer to FIG. 2(b), which is a schematic diagram showing both an oscillation frequency and a resistance for a temperature change in the internal oscillator in FIG. 2(a). As shown, the curve U21 denotes the resistance Q2 for the temperature change, and the curve Y21 denotes the oscillation frequency f2 for the temperature change. The oscillation frequency f2 decreases when the resistance Q2 increases; conversely, the oscillation frequency f2 increases when the resistance Q2 decreases.
In order that the reference current close in magnitude can be provided in different temperatures, which causes each stage of the oscillator to keep the charge and the discharge rates without change for the temperature change, to achieve the object that the oscillation frequency does not drift for the temperature change, a more effective temperature compensating circuit is demanded.